1. Field of the Invention
The present invention pertains to signal synchronization. More particularly, this invention relates to generating a pulse clock signal for the first stage of a synchronizer.
2. Background
Computer technology is continuously advancing, resulting in modern computer systems which provide ever-increasing performance. As computer systems become more advanced, more and more components are being added to computer systems and the number of transistors within these components is ever-increasing.
One artifact of increasing computer system components and transistors is the generation of multiple clock signals. Different components within the computer system are typically driven by (also referred to as "referenced to") clock signals having different frequencies. Components which are driven by a particular clock signal are referred to as operating in the clock domain of that particular clock signal.
In addition, different functional blocks within the components may also be driven by clock signals having different frequencies. For example, a computer system may include a processor coupled to a bus and an interrupt controller, where the interrupt controller generates signals on a serial bus which is referenced to a first clock signal, the bus is referenced to a second clock signal, and the processor core is referenced to yet a third clock signal.
Synchronizers are typically used in computer systems to allow different components operating in different clock domains to communicate with one another. When a component operating in a first clock domain sends a signal to a component operating in a second clock domain, the signal is sent through a synchronizer so that the timing of the signal is synchronized to the second clock domain.
Typically, synchronizers ensure that a signal received by the synchronizer is passed to the targeted clock domain to be seen by the targeted component. However, due to the synchronization process, synchronizers typically do not ensure that the signal will be seen by the targeted component on a particular clock edge. For example, data which comes to the synchronizer close to an edge of the targeted clock domain's clock signal will be seen by the targeted agent either on that clock edge or on the next clock edge. However, a guarantee of which clock edge the data will be seen on cannot typically be made.
In many circumstances, the exact timing of a signal being synchronized is not critical. For example, assume an interrupt controller is operating in a first clock domain and is asserting an interrupt signal to a processor coupled to a bus, and that the bus is operating in a second clock domain. The interrupt signal is synchronized to the bus clock domain by a synchronizer for interpretation by the processor. Timing of the interrupt signal is not critical in this example because the processor functions properly regardless of whether it receives the interrupt signal on a first clock pulse or on the subsequent clock pulse.
However, in some situations, the exact timing of a signal being synchronized is critical. For example, some computer systems operate in a functional redundancy checking (FRC) mode. In FRC mode, one processor (referred to as a checker processor) operates to check the performance of a second processor (referred to as a master processor). The checker processor receives the same signals from the bus as the master processor and performs the same calculations as the master processor. The checker processor, however, does not output signals on the bus. Rather, the checker processor compares the output signals it would place on the bus to the outputs the master processor does place on the bus. Since the master and checker processors are operating according to the same inputs, a discrepancy between what the checker processor would output and what the master processor does output indicates an error was made by one of the two processors. If such a discrepancy arises, then the checker processor asserts an FRC error signal to indicate that all error has occurred.
Thus, it is important that the two processors operating in FRC mode operate in lock-step. That is, signals received on a particular clock edge by one processor need to be received on the same clock edge by the second processor in order to avoid an improper FRC error signal. However, as discussed above, synchronizers typically do not guarantee that data will be seen by the targeted component on a particular clock edge. Therefore, the master processor could receive the signal on one clock edge and the checker processor could receive the signal on the subsequent clock edge. Thus, it would be beneficial to provide a mechanism for ensuring that signals provided by a synchronizer are available on a particular clock edge.
One method which could be used to resolve the synchronization problem between the first and second clock domains is to enforce very stringent timing requirements on the two clock domains when operating in a mode which requires a guarantee of when a signal will be seen (e.g., when operating in FRC mode). However, such stringent requirements create significant difficulties and expenses for system designers. These requirements are made even more difficult to satisfy due to slight differences in timing as a result of process, voltage, and temperature variances. Thus, it would be beneficial to provide a mechanism which ensures signals provided by a synchronizer are available on a particular clock edge without overburdening system designers. Additionally, it would be beneficial to provide a mechanism which ensures signals provided by a synchronizer are available on a particular clock edge, while at the same time does not adversely affect system performance in modes which do not require signals provided by a synchronizer to be available on a particular clock edge.
Furthermore, many integrated circuit (IC) devices include large numbers of transistors. The design and construction of such IC devices is both time and cost intensive. Additionally, stocking larger numbers of different types of IC devices results in increased costs. Thus, it would be beneficial to provide a mechanism which provides consistent synchronization in both systems which require synchronizers to provide signals on a particular clock edge and systems which do not require synchronizers to provide signals on a particular clock edge.
The present invention provides for these and other advantageous results.